Operator Manual

1. Power and connect

• Turn off the power supply before connecting any cables.
• Connect the GND (negative) cable from the PSU to the hashboard.
• Connect the positive cable from the PSU to the hashboard.
• Finally, connect the tester's signal connector to the hashboard.
• Turn on the hashboard's power supply.
• Turn on the tester (USB).

2. Web Interface

On first use (without configured network), the tester creates its own Wi-Fi network:

Connect your phone or PC to this network and open the address in your browser. If already connected to your local network, use the IP displayed on the OLED screen.

Hostname access (mDNS) — no need to remember the IP

When the tester is connected to your local Wi-Fi network (STA mode), besides the IP it also answers on a fixed .local hostname, generated from the last 3 bytes of the tester's eFuse MAC:

This address does not change even if DHCP reassigns the tester's IP after a reboot — useful on benches with multiple testers, since each one gets a unique hostname. When connecting the tester to a Wi-Fi network (Config tab → Wi-Fi), the overlay shown before the AP turns off displays both the new IP and the matching .local URL.

3. Model selection

Upon connecting the hashboard, the tester reads the EEPROM and selects the model automatically in ~2.6 seconds. If not recognized, select it manually in the dropdown.

[+] Legacy EEPROM

NBS1902, NBP1901 and NBS2003 use Bitmain's Legacy format. The NBS1902 is detected automatically. If it appears as LEGACY011, select manually.

4. Signal Flow Panel

Left side panel with visual indicators of physical signals during testing. All signals use a 1.2V LDO.

Click any signal to see a wave flowing through the chips on the grid. Use the Signals button on the topbar to show/hide the panel.

5. Chip map

• OK — passed
• Fail — did not respond
• Unstable — intermittent
• Waiting
• Boost — step-up circuit

Hover over a chip to see: number, domain, nonces/ACKs, and failures. The map updates automatically after each test without reloading the page.

6. Recommended test flow

Each subsequent test assumes the previous one passed. Use LiveScan only for quick visual diagnostics before starting formal tests. CoreCheck and FullLoad may not be available depending on the detected model — see the availability table at the top of this manual.

7. LiveScan

Continuous reading of the chain in near real-time. Does not execute load patterns — only light read-id/ping. Sensors are read at start and updated periodically.

When to use

• Diagnosing bad contacts, missing chips, or unstable chains
• Checking how many chips respond on a board with known defects
• First contact with an unknown hashboard

LiveScan does not replace formal tests for board approval.

8. ChainCheck

Chain test: turns on the PIC (when present), resets the hashboard, reads the EEPROM, detects chips, prepares the chain, and runs 8 verification patterns. Each chip must deliver at least 6 valid responses within the 24-second test window.

Chips that failed appear in red on the map.

9. CoreCheck

Rigorous core test. Runs 3 independent load-pattern cycles. Each cycle is evaluated separately — a chip that fails in any cycle fails the whole test. Detects chips that pass ChainCheck but are unstable under sustained load.

The chip map shows the accumulated response count across the 3 cycles. A chip with 8+10+0 shows "18" and turns red (failed cycle 3 with 0 responses).

[+] BM1362 ACK mode: for JPro/BM1362 hashboards, CoreCheck counts reception acknowledgements (ACKs) instead of SHA256 nonces. A chip that ACKs in all 3 cycles is healthy. The criterion looks simple (1 ACK), but the 3 independent cycles catch chips that only respond intermittently — something a single 24s cycle would not detect.

[+] Temperature: sensors are read on every pattern with a lightweight protocol. The test aborts automatically if temperature exceeds 70°C.

10. FullLoad

Full-load validation at the chip's operating frequency (read from EEPROM when available; otherwise falls back to the profile default). Requires all chips on the board to respond in each cycle. The test repeats job cycles for the number selected in the modal.

Progress Modal

[+] Tip: Closing the modal does not stop the test. To reopen, click the FullLoad button (orange) again in the topbar while the test is running. Use Stop inside the modal or in the topbar to cancel.

Approval Criteria

How FullLoad works by ASIC

[+] FullLoad for BM1362 uses the same ACK mechanism as CoreCheck, but at the EEPROM operating frequency and requiring 100% of chips. It is the final proof that every chip in the chain is functional at that frequency.

Expected Nonce Distribution (BM1398P)

11. Temperature

Normal ranges: intake 30–50°C, exhaust 60–85°C. -- = sensor did not respond.

12. Stop a test

Click Stop on the topbar at any time. The state of the chips up to that point is preserved on the map.

13. EEPROM Editor

Click the EEPROM button on the topbar to access the editor.

Restore from computer

1. Select the backup file (.bin, 256 bytes) — decoded data appears (Serial, Model, Freq, Volt, CRC).
2. Choose which fields to restore: Frequency and voltage (always restored) and, optionally, Board serial.
3. Click Restore selected fields.

14. Config (gear icon)

Wi-Fi Tab

• Click Scan networks
• Select the SSID and enter the password
• Click Connect — the tester saves and reconnects automatically on the next boots

Firmware Tab (OTA)

• Click Choose file
• Select a .bin file: update_vX_Y.bin (full bundle, firmware + interface) or firmware.bin (firmware only). Type is auto-detected
• Click Send and update
• Wait for the bar to complete — the tester restarts automatically

License Tab

Shows the active plan and which features are enabled: basic tests, EEPROM read/editor, advanced tests, FullLoad, firmware updates, and PDF report. To install a license, select the .britlic file issued by the management portal and click Install license.

Without a valid license, protected buttons remain hidden or locked. The license is bound to the tester's eFuse MAC.

15. Event Log

16. Troubleshooting

17. Signal Diagnostics (Bitmain)

Troubleshooting sequence (0 chips)

• Power supply voltage (main)
• Domain voltage (~0.32V per chip)
• PIC output (~3.2V on U6 pin 11)
• Boost voltage (20V)
• 1.2V and 0.8V LDO per domain
• CLK/TX/RX/RST signals

[+] Dichotomic Method
Divide the chain in half and measure RO/1.2V at the midpoint to isolate which half has the problem. Repeat until you find the chip.

18. Flow Summary

• 1. Connect: GND → +V → signals → power on tester
• 2. Open http://192.168.4.1 on mobile/PC
• 3. Model auto-detected (~2.6s) or select from dropdown
• 4. LiveScan → optional, quick visual diagnostic
• 5. ChainCheck → validate chain (24s, 8 patterns, 6 responses/chip)
• 6. CoreCheck → validate cores (72s, 3 cycles, 12 responses/chip/cycle) — availability depends on model
• 7. FullLoad → validate load at operating frequency (100% of chips required) — availability depends on model
• 8. EEPROM → read, edit, backup, or clone when necessary
• 9. Disconnect: signals → +V → GND