Operator Manual

Brit Tester v0.7.0 Documentation

The Brit Tester is a portable workbench for diagnosing and validating Antminer hashboards. Connect the hashboard, open the web interface, and run the tests. Results appear in real-time.

✅ Validated Models

S19/T19 76C (BM1398P) • S19 Pro 114C (BM1398P) • S19j Pro 120C and 126C (BM1362) • S19k Pro 77C (BM1366) • S19 XP (BM1368) • S19i (BM1360)

1. Power and connect

⚠ Mandatory sequence

Connect: GND → +V → signals. Disconnect in reverse order: signals → +V → GND. Failing to follow this order may damage the hashboard's level shifters.

2. Web Interface

On first use (without configured network), the tester creates its own Wi-Fi network:

ParameterValue
SSIDBritTester
URLhttp://192.168.4.1

Connect your phone or PC to this network and open the address in your browser. If already connected to your local network, use the IP displayed on the OLED screen.

🔒 Unauthorized hardware

If the equipment is not provisioned, a block page will appear with the ESP32 eFuse MAC. Send the MAC to support for provisioning.

3. Model selection

Upon connecting the hashboard, the tester reads the EEPROM and selects the model automatically in ~2.6 seconds. If not recognized, select it manually in the dropdown.

Board CodeTester ModelASIC
NBS1902S19/T19 76CBM1398P
NBP1901S19Pro 114CBM1398P
BHB42601/42621/42631S19JPro 126CBM1362
BHB42611/42612S19JPro 120CBM1362
BHB56902/56903S19kPro 77CBM1366
NBS2003S19i 80CBM1360

🔌 Legacy EEPROM

NBS1902, NBP1901 and NBS2003 use Bitmain's Legacy format. The NBS1902 is detected automatically. If it appears as LEGACY011, select manually.

4. Signal Flow Panel

Left side panel with visual indicators of physical signals during testing. All signals use a 1.2V LDO.

SignalASIC NameDirectionIdleOperation
TXCI (Command In)Chip 1 → N0V1.2V
BIBO (Broadcast Out)Chip 1 → N0V0V (always)
RSTResetChip 1 → N0V1.2V (pulse)
CLKXIN (Clock)Chip 1 → N0.5–0.6V
RXRI/RO (Response)Chip N → 10.3V1.2V

Click any signal to see a wave flowing through the chips on the grid. Use the Signals button on the topbar to show/hide the panel.

5. Chip map

Hover over a chip to see: number, domain, nonces/ACKs, and failures. The map updates automatically after each test without reloading the page.

6. Recommended test flow

LiveScan (optional) → Basic Pattern → Pattern+ Test → Pattern 2 Test → Mining

Each subsequent test assumes the previous one passed. Use LiveScan only for quick visual diagnostics before starting formal tests.

7. LiveScan

Continuous reading of the chain in near real-time. Does not execute load patterns — only light read-id/ping. Sensors are read at start and updated periodically.

When to use

LiveScan does not replace formal tests for board approval.

8. Basic Pattern (Scan)

Chain test: turns on PIC, resets hashboard, reads EEPROM, detects chips, prepares chain, and executes basic verification. Does not send hashing jobs — only detects chips.

Basic Pattern Test | PASS | 126 / 126 OK Basic Pattern Test | FAIL | 25 / 126 OK

Chips that failed appear in red on the map.

9. Pattern+ Test

Executes extensive patterns per chip using vectors from the SD card when available. Detects chips that pass Basic Pattern but fail under different work patterns.

⚕ Cooling required

Confirm the fans are on before starting. The warning modal opens automatically.

Pattern+ Test | PASS | 126 / 126 OK Pattern+ Test | FAIL | 98 / 126 OK

📄 SD Card

If no vector files are available on the SD, the test uses a reduced internal coverage. The log warns when this happens.

10. Pattern 2 Test

Alternative cycle requiring real SHA256 nonce. A board that passes Basic Pattern but fails here has marginal chips — they work in basic patterns but are unstable under real load.

⚕ Cooling required

Confirm the fans are on before starting.

Pattern 2 Test | PASS | 126 / 126 OK Pattern 2 Test | FAIL | 110 / 126 OK

11. Mining

Full load with real SHA256 jobs (full-header). Approves only chips that return a valid SHA256 nonce (type4). Each cycle runs until 99.5% of chips deliver at least 3 nonces.

⚕ Adequate cooling required

Confirm fans are on. Select the number of cycles in the modal before starting.

Progress Modal

FieldDescription
Theoretical THTheoretical capacity (freq x cores x OK chips)
Nonces/sActual rate of nonces delivered in the current cycle
OK ChipsChips with at least 3 valid nonces
ErrorsChips that haven't reached the minimum yet
FreqFrequency applied to the PLL

💡 Tip: Closing the modal does not stop the test. To reopen, click the Mining button again in the topbar while the test is running.

Frequency by model

ASICFrequencyModel
BM1362465 MHzS19j Pro
BM1366650 MHzS19k Pro
BM1368650 MHzS19 XP
BM1398P525 MHz*S19 / S19 Pro
BM1360525 MHzS19i

* S19/T19 76C limited to 650 MHz even if EEPROM reports a higher value.

Approval Criteria

ParameterValue
Minimum nonces per chip3
Required OK chips99.5% of total
Example 126 chips125 OK chips (allows 1 failure)
Example 76 chips75 OK chips (allows 1 failure)

Expected Nonce Distribution

Nonces in cycleInterpretation
≥ 10Normal — healthy chip
5 – 9Slightly low — monitor
3 – 4Borderline — potentially marginal chip
1 – 2Below minimum — failed
0Dead or disconnected chip

A variation of 5 to 28 nonces among chips in the same cycle is normal — SHA256 has a random component by design.

12. Temperature

PanelSensorPosition
Top right0x48Air exhaust — top
Bottom right0x49Air exhaust — bottom
Top left0x4AAir intake — top
Bottom left0x4BAir intake — bottom

Normal ranges: intake 30–50°C, exhaust 60–85°C. -- = sensor did not respond.

13. Stop a test

Click Stop on the topbar at any time. The state of the chips up to that point is preserved on the map.

14. EEPROM Editor

Click the EEPROM button on the topbar to access the editor.

FieldEditableDescription
SerialYesSerial number (up to 18 characters)
BoardNoBoard code (e.g., BHB42601)
ASICNoChip model (e.g., BM1362)
Freq (MHz)YesProgrammed operating frequency
Volt (mV)YesProgrammed operating voltage
CRC Pt1/Pt2Nostored = calculated = OK. Mismatch = Corrupted EEPROM
ButtonFunction
Save backup (NVS)Saves a copy in the tester's internal memory
Restore backup (NVS)Recovers the saved copy to overwrite
Read to clone / Write cloneClones EEPROM between two hashboards

⚠ Attention

Always save a backup before editing. Never alter unknown calibration settings blindly.

15. Config (gear icon)

Wi-Fi Tab

SD Tab

Shows if the SD is mounted and which vector files are available. OK = external file present. internal fallback = SD mounted but without external file; firmware uses built-in vector.

Test Tab

Defines the number of Basic Pattern cycles (3, 5, 10, or 20).

Visual Tab

Interface color palette selection (Current / Modern / Industrial). Saved in browser, does not alter firmware.

Firmware Tab (OTA)

16. Event Log

Color (App)Type
BlueInformation
GreenSuccess
OrangeWarning
RedError

17. Troubleshooting

SymptomWhat to check
Blank pageReflash SPIFFS via cable or send spiffs.bin
Model not detectedEEPROM didn't respond — select manually
0 chips detectedBoost (20V), domain voltage (0.32V/chip), PIC, level shifters
Temperature shows --Hashboard powered? PIC initialized?
All chips redCorrect model? Power, RST, and UART OK?
Mining stuck at 0%Hashboard must pass Basic Pattern first
Pattern+ / PT2 with raw_bytes=0Check amperage — requires minimum 60A for SHA256
CRC Pt1/Pt2 mismatchCorrupted EEPROM — do not write without investigating
"Unauthorized hardware" appearsSend the displayed eFuse MAC to support for provisioning
SD fails to mountCard inserted? Class 10+? Tester auto-retries 3x on boot

SD Card Errors

Timeout (0x107)

sdmmc_read_sectors_dma: sdmmc_send_cmd returned 0x107

Card poorly inserted, dirty contacts, or defective. Remove, clean, and reinsert.

File not found (errno=22)

Expected folder: /BM1362-pattern/pattern_8midstate.bin or /reference/BM1362-pattern/. BM1362 Mining doesn't depend on SD — uses internal job.

18. Signal Diagnostics (Bitmain)

Abnormal SignalProbable Cause
CLK < 0.5VDamaged crystal oscillator or broken chip
RST doesn't rise to 1.2VLevel shifters (U1/U3/U4) or short circuit
TX (CI) missingDamaged level shifter or stuck chip
RX (RO) missingChip at the end not responding; check R232/R233 (S19 Pro) or R8/R9 (S19)
BI (BO) not 0VChip with a short on the broadcast signal

Troubleshooting sequence (0 chips)

💡 Dichotomic Method
Divide the chain in half and measure RO/1.2V at the midpoint to isolate which half has the problem. Repeat until you find the chip.

19. Flow Summary

20. Adapter Board Pinout

SignalESP32-S3 GPIO
RST (Hashboard reset)GPIO 10
PLUG0 (connection detect)GPIO 11
I2C SDA (PIC/EEPROM)GPIO 8
I2C SCL (PIC/EEPROM)GPIO 3
UART TX (to ASIC)GPIO 17
UART RX (from ASIC)GPIO 18
POWER_ENFixed 3V3 (no ESP GPIO)

Pinout validated on workbench for BHB42601/BM1362/126 chips. I2C at 30 kHz.